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Scott, MIT Graduate
Category: Homework
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Experience:  MIT Graduate (Math, Programming, Science, and Music)
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Design a modulo-6*. D Type, Asynchronous down counter in

Customer Question

Attachment: 2016-09-22_153230_design_a_modulo_countdown_timer.doc

Design a modulo-6*. D Type, Asynchronous down counter in which gated outputs reset the bistables after the appropriate count is achieved. Test the design on PSpice (downloaded programme) Show designs working give screen shots of appropriate wave forms (*modulo-6 5, 4, 3, 2, 1, 0, 5, 4, 3, 2, 1, 0, ……5, 4,

Submitted: 1 year ago.
Category: Homework
Expert:  Bruce Wilner replied 1 year ago.

Hi. I can help you with this.

You didn't state how you wanted it designed. What types of gates (I presume you wanted a gate-level design)? Did you need documentation of a Mealy or Moore automaton?

Please note offer of premium service. This is not just a quick toss-up question.

Expert:  Bruce Wilner replied 1 year ago.

I am still awaiting your feedback. Also, you didn't indicate whether you want the clocked sequential nature to be implemented with D, T, SR, or JK flip-flops.

Expert:  Bruce Wilner replied 1 year ago.

If you're still interested in having this assignment completed, I will be back in the morning, east coast U.S. time, approx. 1300 London time. Thank you for your patience and forbearance.

Customer: replied 1 year ago.

Good morning Bruce.

Firstly please accept my sincere apologies for not responding sooner, I posted the question from my workplace where I have my internet connection.

Regarding your clarification questions, I am assuming as basic as possible using PSpice, Asynchronous as stated in the question is hard enough for me to understand!

Gated output is stated in the question but I'd be guessing on what type, as long as I can show screen shots or print out of different phases of a working timer on PSpice I'm sure that would suffice.

Again, thank you for your assistance with this.

Kind regards

Expert:  Bruce Wilner replied 12 months ago.

PSPICE? I'm a real engineer. I don't believe in it. I thought you wanted an ACTUAL CIRCUIT designed with, like, logic gates and flip-flops.

Was I incorrect?

I see you rejected the offer. I can't do all this within the committed scope. It's straightforward enough, but it's focused digital electronics expertise, not help-desk support. My apologies.

Customer: replied 12 months ago.

Hi Bruce,

I'm an aged time served mechanical technician, this is all way above me, its just a university question, I hardly understand it at all, all I do know it has to be on PSpice as stated.

Does accepting the offer get me a PSpice answer or should I re-list the question and hope for the best?


Expert:  Bruce Wilner replied 12 months ago.

I would relist and hope for the best.

That is, depending on what the role of PSPICE in this analysis is.

To simulate in PSPICE requires a lot more than just designing the circuit: I would have to select actual chips, fiddle with all the pin-outs, etc. That's a GREAT DEAL of work, not just a mathematical exercise in drawing some Karnaugh maps and reducing flip-flop input functions to minimal implicant expansions.

Customer: replied 12 months ago.

Hi Bruce,

Is obvious how little I understanding I have of the subject, I was thinking that the attached circuit layout was the catalyst for the question and some basic fiddling from there on.

What can I say, thank you for your time.


Expert:  Bruce Wilner replied 12 months ago.

I see you have been back here several times.

I would be delighted to design the circuit for you. I will leave the PSPICE simulation for someone else.

Doesn't anyone just build circuits in the lab any more out of actual gates on a breadboard?

You would have to create another task. Please list it under COMPUTER, NOT under HOMEWORK, so it goes to me or another putative digital expert, not to a schoolteacher!

Thank you for your patience and forbearance.

Customer: replied 12 months ago.

Good afternoon Bruce (BST)

Unfortunately I need to answer the question as written and not deviate into the real world, attached is my attempt so far which at present fails to function properly.

I appreciate your offer to do the right thing but it's not the actual answer to the question.


Attachment: 2016-09-27_131231_pspice_12.doc

Expert:  Bruce Wilner replied 12 months ago.

Who designed all that? What are U1 and U4 and such? We need DOCUMENTATION.

This could've been realized much more simply with SR flip-flops.

The reason? Remember the DON'T CARE state (S = R = 1) makes the Karnaugh maps simpler in general.