Homework

Homework

# 1. (TCO 3) What is the basic logic function that generates

a LOW only if all...
1. (TCO 3) What is the basic logic function that generates a LOW only if all of its digital inputs are LOW? (Points : 7)
AND
OR
NOT
NAND

2. (TCO 3) What is the result when 9F016 is decremented by 1? (Points : 7)
9E916
9EF16
9F916
9F116

3. (TCO 3) What is the result of the binary subtraction 1100 – 0110? (Points : 7)
0010
0101
1010
0110

4. (TCO 3) What is the minimum number of select lines required for an 8-to-1 demultiplexer? (Points : 7)
1
3
8
24

5. (TCO 3) If the inputs to a one-bit full-adder are A = 1, B = 0, Cin =1, what are the outputs? (Points : 7)
Σ = 0, Cout = 0
Σ = 1, Cout = 0
Σ = 0, Cout = 1
Σ = 1, Cout = 1

6. (TCO 3) The decimal number 25 is equal to what binary number? (Points : 7)
10001
10011
10101
11001

7. (TCO 3) What is the largest number that can be represented by 10 bits? (Points : 7)
512
1023
1024
2048

8. (TCO 3) Which logic gate implements the Boolean expression:C:\Users\D01642558\Desktop\SEPT12\Course Development\ECET299\docs\Edited Exams\images\w11q10.gif ? (Points : 7)
AND
OR
NAND
NOR

9. (TCO 3) How many bits are required to represent decimal numbers from -32,768 to +32,767? (Points : 7)
10
15
16
18

10. (TCO 3) A multiplexer has four data select lines, A3-A0. What is the multiplexer configuration? (Points : 7)
4-to-1
8-to-1
16-to-1
32-to-1

11. (TCO 3) If an input to a 3-input NAND gate is shorted to ground, the output is (Points : 7)
HIGH.
LOW.
switching.
unknown.

12. (TCO 3) A D-type flip-flop is triggered with a rising edge clock. If the flip-flop is set, what condition will causes the flip-flop to reset? (Points : 7)
CLK = ­, D = 0
CLK = ­, D = 1
CLK = ¯, D = 0
CLK = ¯, D = 1

13. (TCO 3) A periodic signal is HIGH for a time ton and LOW for a time toff. The formula for duty cycle is (Points : 7)
.
.
.
.

14. (TCO 3) The primary purpose of a resistor in series with a LED being driven by a flip-flop is to (Points : 7)
limit voltage.
limit current.
limit speed.
limit power.

15. (TCO 3) The group of bits 10110101 is serially shifted (right-most bit first) into an 8-bit
parallel output shift register with an initial state of 11100100. After two clock pulses, the register contains (Points : 7)
01011100.
10110101.
01111001.
00101101.

16. (TCO 3) A MOD-5 and a MOD-20 counter are cascaded. What is the output frequency if the input frequency is 60 MHz? (Points : 7)
6 MHz
2.4 MHz
600 kHz
240 kHz

17. (TCO 3) Select the FPGA look-up table for a 2-input NAND gate. (Points : 7)
C:\Users\D01642558\Desktop\SEPT12\Course Development\ECET299\docs\Edited Exams\images\w11q53a.gif

C:\Users\D01642558\Desktop\SEPT12\Course Development\ECET299\docs\Edited Exams\images\w11q53c.gif
C:\Users\D01642558\Desktop\SEPT12\Course Development\ECET299\docs\Edited Exams\images\w11q53d.gif

18. (TCO 3) How many logic states does a MOD-16 counter have? (Points : 7)
15
16
17
32

19. (TCO 3) Select the FPGA look-up table for a 1-bit half-added with a data inputs A and B, sum out S, and carry out C. (Points : 7)

20. (TCO 3) In VHDL, what are the allowed outputs for a BIT signal type? (Points : 7)
0, 1
true, false
-231 to +231
0, 1, Z

21. (TCO 3) The VHDL signal assignment statement for a 4-input NAND gate is (Points : 7)
X = not(A or B or C or D);.
X <= not A and not B and not C and not D;.
X = not(A and B and C and D);.
X <= A nand B nand C nand D;.

22. (TCO 3) A VHDL design file includes the following statement for a counter: “Q <= Q + 1.” What signal type is the signal Q? (Points : 7)
IN
OUT
INOUT
BUFFER

23. (TCO 3) A state diagram for a MOD-16 counter is drawn with 16 bubbles. If the lines connecting the bubbles have arrowheads on both ends, what can we say about the counter? (Points : 7)
Nothing, because the drawing is in error.
This represents a 4-bit up-down counter.
This represents a 16-bit binary counter.
This represents a 4-bit ring counter.

24. (TCO 3) How many state variables are in a MOD-27 counter? (Points : 7)
27
5
26
4

25. (TCO 3) Which of the following is not a state machine? (Points : 7)
MOD-6 counter
4-bit shift register
8-bit register
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2/27/2013
R.R. Jha, Tutor
Category: Homework
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Hi,
Welcome!

I'm working on this, would finish it and get back to you asap.

Thanks
Customer reply replied 4 years ago
Ok
Ok, it should take about half an hour or so.
Image is missing in question 8 and 17. Please take a screenshot of the problem with images, paste them in a word file. Then upload the file at wikisend.com or mediafire.com, and post its download link here. Let me know.

Thanks
Customer reply replied 4 years ago
Don't worry about 8 and 17. I got that. I need the rest ASAP. THANKS
Ok, sure!
Options given in question 12 and 13 are also not clear
Customer reply replied 4 years ago
Do all that you can
Ok
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R.R. Jha, Tutor
Category: Homework
Satisfied Customers: 5,471
Experience: B.Tech
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Satisfied Customers: 5,471
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