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# FPGA placement using Simulated Annealing or any other methods.

### Customer Question

FPGA placement using Simulated Annealing or any other methods. given an input file, place the inputs, outputs and gates.
INPUT file format
L5
INPUT_SIGNAL(CLK)
INPUT_SIGNAL(CLK)
INPUT_SIGNAL(CLK)
INPUT_SIGNAL(CLK)
INPUT_SIGNAL(E4)
INPUT_SIGNAL(E5)
INPUT_SIGNAL(E6)
INPUT_SIGNAL(E7)
INPUT_SIGNAL(E111)
INPUT_SIGNAL(D15)
INPUT_SIGNAL(D16)
INPUT_SIGNAL(D18)
INPUT_SIGNAL(D19)
OUTPUT_SIGNAL(E15)
OUTPUT_SIGNAL(E16)
OUTPUT_SIGNAL(E17)
OUTPUT_SIGNAL(E18)
OUTPUT_SIGNAL(E19)
E10 = NOT(E2)
E0 = DFF(D15, CLK)
E13 = NOT(E9)
E18 = NAND3(E14, E15, E13)
E1 = DFF(D16, CLK)
E14 = NOT(E10)
E9 = NOR2(E1, E2)
E3 = DFF(D19, CLK)
E8 = NAND3(E0, E1, E5)
E12 = NOT(E8)
E15 = NOR4(E10, E11, E7, E111)
E16 = XOR2(E12, E13)
E17 = NOT(E13)
E19 = NOT(E15)
E11 = NAND4(E6, E4, E3, E2)
E2 = DFF(D18, CLK)
OUTPUT file format
L1
INPUT_SIGNAL(A1) 48
INPUT_SIGNAL(A2) 47
INPUT_SIGNAL(A3) 46
INPUT_SIGNAL(A4) 44
INPUT_SIGNAL(A5) 42
INPUT_SIGNAL(A6) 41
INPUT_SIGNAL(A7) 40
INPUT_SIGNAL(A8) 39
INPUT_SIGNAL(A9) 38
INPUT_SIGNAL(A10) 37
INPUT_SIGNAL(A24) 10
INPUT_SIGNAL(A25) 11
INPUT_SIGNAL(A19) 30
INPUT_SIGNAL(A240) 27
INPUT_SIGNAL(A250) 26
OUTPUT_SIGNAL(A14) 32
OUTPUT_SIGNAL(A26) 14
OUTPUT_SIGNAL(A27) 17
OUTPUT_SIGNAL(A28) 19
OUTPUT_SIGNAL(A29) 23
A11 = NAND3(A1, A2, A3) 1 1
A12 = NOT(A4) 1 2
A13 = NOR3(A5, A6, A7) 1 3
A14 = NAND4(A7, A8, A9, A10) 1 4
A15 = NOR3(A11, A12, A13) 2 1
A16 = NAND2(A12, A13) 2 2
A17 = NOT(A13) 2 3
A18 = XOR2(A13, A14) 2 4
A20 = NAND2(A15, A16) 3 1
A21 = NOT(A16) 3 2
A22 = NAND4(A13, A16, A17, A18) 3 3
A23 = NAND2(A18, A19) 3 4
A26 = NAND3(A20, A24, A25) 4 1
A27 = NOR2(A21, A20) 4 2
A28 = NAND2(A22, A27) 4 3
A29 = NOR4(A240, A250, A23, A28) 4 4
Submitted: 1 year ago.
Category: Homework
Expert:  Mr. Gregory White replied 1 year ago.
Hello, my name is Greg.
I see this might be time sensitive.
Do you still need this answered?