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ATLPROG, Computer Software Engineer
Category: Programming
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Experience:  MS in IT.Several years of programming experience in Java C++ C C# Python VB Javascript HTML
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Comp Architecture - Pipelining Design. Please see attached

Customer Question

Comp Architecture - Pipelining Design.
Please see attached file.
Submitted: 14 days ago.
Category: Programming
Expert:  Bruce Wilner replied 14 days ago.

There is no attached file.

Expert:  Bruce Wilner replied 14 days ago.

I will be back in nine hours to check for one.

Customer: replied 14 days ago.
Attached file.
Expert:  Bruce Wilner replied 14 days ago.

Thanks. A picky point, but one worth noting anyway: are we implicitly assuming that all instructions take the same amount of time to execute--regardless of the fact that, for example, a move with two deferred operands requires multiple memory fetches?

One is typically forbidden to ask such questions: it's, like, MAGIC. But--once upon a time, when CPUs were implemented by Brontosauruses gated in and out of two neighboring paddocks, one representing "0", the other representing "1"--one had to consult a processor handbook to determine how many cycles are ACTUALLY required for the evaluation of non-immediate, non-register operands. (We used to hang cards around the brontos' necks that matched the FORTRAN variable names. For integers, a young twenty-footer would suffice; when word length was increased to 64 bits, we had to introduce the Diplodocus.)

Of course, this can be swept under the rug by actually implementing "memory" as an independent co-processor that operates at a much faster clock rate--such that the slowest possible instruction, perhaps a three-operand instruction with all operands multiply deferred, fits within one "CPU cycle" in the large.

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